1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to a semiconductor memory device capable of rewriting a data signal.
2. Description of the Background of Art
FIG. 20 is a circuit block diagram showing a main section of a prior art dynamic random access memory (hereinafter referred to as DRAM).
In FIG. 20, this DRAM has two memory cell arrays MA1 and MA2. Each of memory cell arrays MA1 and MA2 includes memory cells MC located at respective intersections between word lines WL and bit line pairs BL and /BL. Memory cell MC stores one data signal thereon.
Bit line equalize circuits 82 and 83 are provided to bit line pairs BL and /BL of respective memory cell arrays MA1 and MA2. Bit line equalize circuits 82 and 83 are activated in response to transition of respective bit line equalize signals BLEQL and BLEQR to L level, which is an active level, to precharge corresponding bit line pair BL and /BL to bit line precharge potential VBL (=VCC/2).
A transfer gate 80 is provided between a pair of bit lines BL and /BL of memory cell array MA1 and a pair of nodes N81 and N82; and a transfer gate 81 is provided between a pair of bit lines BL and /BL of memory cell array MA2 and a pair of nodes N81 and N82. Transfer gates 80 and 81 become non-conductive in response to transition of signals BLIL and BLIR to L level.
Nodes N81 and N82 are connected to a sense amplifier 84. Sense amplifier 84 is activated in response to transition of sense amplifier activation signals SE and /SE to H level and L level, respectively, to amplify a small potential difference occurring between nodes N81 and N82 to power supply voltage VCC. Nodes N81 and N82 are connected to one ends of global IO lines GIO and /GIO through a column select gate 85. Column select gate 85 becomes conductive in response to transition of a corresponding column select line CSL to H level, which is a select level.
A GIO line equalize circuit 86, a read amplifier 87 and a write driver 88 are connected to the other ends of global 10 line pair GIO and /GIO. GIO line equalize circuit 86 is activated in response to transition of GIO line equalize signal GIOEQ to L level, which is an active level, to precharge global IO lines GIO and /GIO to power supply potential VCC. Read amplifier 87 is activated in response to transition of a signal PAE to H level, which is an active level, to compare potentials of global lines GIO and /GIO in magnitude with each other and to output a read data signal RD at a logical level corresponding to a result of the comparison.
Write driver 88 is activated in response to transition of a write driver activation signal WDE to H level, which is an active level, to drive one of global IO lines GIO and /GIO to H level and in addition, the other to L level according to a logical level of a write data signal WD.
That is, write driver 88, as shown in FIG. 21, includes: NAND gates 91 and 92; inverters 93 to 97; P channel MOS transistors 98 and 99; and N channel MOS transistors 100 and 101. P channel MOS transistors 98 and 99 are connected between power supply potential VCC line and each of respective global lines GIO and /GIO; and N channel MOS transistors 100 and 101 are connected between each of respective global IO lines GIO and /GIO and ground potential GND line.
Write driver activation signal WDE is inputted to one input nodes of NAND gates 91 and 92. Write data signal WD is inputted directly to the other input node of NAND gate 91 and in addition, to the other input node of NAND gate 92 through inverter 93. An output signal of NAND gate 91 is inputted to the gate of P channel MOS transistor 98 through inverters 94 and 95, and in addition, to the gate of N channel MOS transistor 101 through inverter 94. An output signal of NAND gate 92 is inputted to the gate of N channel MOS transistor 100 through inverter 95 and in addition, to the gate of P channel MOS transistor 99 through inverters 96 and 97.
In write operation and in a case where no rewriting of data is inhibited by a write mask signal, write driver activation signal WD is driven to H level, which is an active level, and NAND gates 91 and 92 operate as inverters. In a case where write data signal WD is at H level, MOS transistors 98 and 101 become conductive and in addition, MOS transistors 99 and 100 become non-conductive, and global IO lines GIO and /GIO are driven to H level and L level, respectively. In a case where write data signal WD is at L level, MOS transistors 99 and 100 become conductive and in addition, MOS transistors 98 and 101 become non-conductive, and global lines GIO and /GIO are driven to L level and H level, respectively.
Then, description will be given of an operation of DRAM shown in FIGS. 20 and 21. Note that of memory cell arrays MA1 and MA2, memory cell array MA1 is selected.
In write operation, bit line equalize signal BLEQL is first raised to H level to deactivate bit line equalize circuit 82 and in addition, array select signal BLIR is driven to L level to cause transfer gate 81 to be non-conductive. Then, word line WL is driven to H level, which is a select level, to activate memory cell MC and a small potential difference occurs between bit line pair BL and /BL according to stored data on memory cell MC.
Then, sense amplifier activation signals SE and /SE are driven to H level and L level, respectively, to activate sense amplifier 84; and one bit line (for example, BL) is driven to H level and in addition, the other bit line (/BL in this case) is driven to L level. Subsequently, GIO line equalize signal GIOEQ is driven to H level, which is an inactive level, and GIO line equalize circuit 86 is deactivated to cease equalization of global IO lines GIO and /GIO.
Then column select line CSL is raised to H level, which is a select level, to cause column gate 85 to be conductive and potentials of bit lines BL and /BL are transmitted to respective global IO lines GIO and /GIO. Read amplifier 87 is activated in response to transition of signal PAE to H level, which is an active level, to compare potentials of global IO lines GIO and /GIO in magnitude and to output read data signal RD at a logical level corresponding to a result of the comparison.
In write operation, similar to a read operation, bit line equalize circuit 82 is deactivated, transfer gate 81 is caused to be non-conductive, sense amplifier 84 is activated to drive one bit line to H level and in addition, the other bit line to L level, and GIO line equalize circuit 86 is deactivated to cease equalization of global IO line pair GIO and /GIO.
Then, write driver activation signal WDE is driven to H level, which is an active level, to activate write driver 88; and one of global IO lines GIO and /GIO is driven to H level, and the other is driven to L level according to a logical level of write data signal WD. Subsequently, column select line CSL is driven to H level, which is a select level, to cause column select gate 85 to be conductive and potentials of global IO lines GIO and /GIO are transmitted to bit lines BL and /BL to write a potential of a bit line (BL in the figure) onto memory cell MC.
In a prior art DRAM, however, bit line pair BL and /BL and global IO line pair GIO and /GIO are connected directly to each other through column select gate 85; therefore, there has been a problem that in a case where precharge of global 10 line pair GIO and /GIO is incomplete, or in a case where noise occurs on global IO line pair GIO and /GIO by interference from other wirings, a data signal read-out onto bit line pair BL and /BL is destroyed. Although there is a method to enhance a current drive ability of sense amplifier 84 as a measure to prevent a data signal read-out onto bit line pair BL and /BL from being destroyed, a problem of increase in a layout area of sense amplifier 84 still remains.
Furthermore, since there has been a necessity for precharge of global IO lines GIO and /GIO performed each time data signal WD is written onto memory cell MC, a time for precharge is necessary, having lead to difficulty in realization of a high speed write operation.
Moreover, in a case where write mask operation is performed, since global IO lines GIO and /GIO are precharged to H level and thereafter, column select gate 85 is caused to be conductive, a current flows out from global IO line GIO or /GIO, whichever has been driven to H level, to bit line BL or /BL, whichever has been driven to L level, having resulted in useless consumption of the current.
Therefore, it is a main object of the present invention to provide a semiconductor memory devices, strong in noise resistance, fast in write operation and low in consumed current.
A semiconductor memory device includes: a memory block including plural memory cells, plural word lines and plural bit line pairs; a sense amplifier amplifying a potential difference occurring between a bit line pair; a row decoder selecting one word line of the plural word lines according to a row address signal; a column decoder selecting one bit line of the plural bit line pairs according to a column address signal; a read data line pair; a write data line pair; a read circuit connected to one ends of the read data line pair; a write circuit connected to one ends of the write data line pair; and an input/output control circuit, coupling a bit line pair selected by the column decoder and the other ends of the read data line pair with each other in read operation, and coupling a bit line pair selected by the column decoder and the other ends of the write data pair with each other in write operation. The input/output control circuit includes: first and second transistors provided to each bit line pair, and whose input electrodes are connected to first and second bit lines, respectively, included in a corresponding bit line pair; a first switch circuit, provided to each bit line pair, and connecting corresponding first and second transistors between each of first and second read data lines, respectively, included in the read data line pair and a line of a first reference potential in response to selection of a corresponding bit line pair by the column decoder in read operation; third and fourth transistors, provided to each bit line pair, and whose input electrodes are connected to first and second write data lines, respectively, included in the write data line pair; and a second switch circuit, provided to each bit line pair, and connecting corresponding third and fourth transistors between each of first and second bit lines, respectively, included in a corresponding bit line pair and a line of a second reference potential in response to selection of a corresponding bit line pair by the column decoder in write operation. Therefore, in write operation, since a bit line pair and the read data line pair are connected indirectly to each other through the input electrodes of the first and second transistors, no data read-out onto the bit line pair is destroyed even in a case where noise occurs on the read data line pair in read operation. Moreover, in write operation, since input potentials of the third and fourth electrodes are controlled through the write data line pair, there is no necessity for precharging of the write data line pair to power supply potential. Accordingly, a high speed write operation can be realized.
Preferably, the first and second transistors are each an N channel MOS transistor and the first reference potential is ground potential. In this case, the first or second transistor corresponding to a bit line on the power supply potential side of the first and second bit lines becomes conductive, and the first or second read data line corresponding to the first or second transistor whichever has become conductive is driven to ground potential.
Preferably, the read circuit includes: a precharge circuit charging the first and second read data lines to power supply potential in advance; and a read amplifier comparing potentials of the first and second read data lines in magnitude to output a data signal at a logical level corresponding to a result of the comparison. In this case, the read circuit can be constructed with ease.
Preferably, the third and fourth transistors are each an N channel MOS transistor and the second reference potential is ground potential. In this case, the third or fourth transistor corresponding to a write data line on the power supply potential side of the first and second read data lines becomes conductive, and the first or second bit line corresponding to the third or fourth transistor whichever has become conductive is driven to ground potential.
Preferably, the write circuit drives one write data line of first and second write data lines to power supply potential and the other write data line to ground potential, according to a logical level of a write data signal; and drives both of the first and second write data lines to ground potential in write mask mode in which rewriting of data is inhibited. In this case, since no current flows out from a bit line pair and the read data line pair in write mask mode, a consumed current remains small in magnitude.
Preferably, the third and fourth transistors are each a P channel MOS transistor and the second reference potential is power supply potential. In this case, the third or fourth transistor corresponding to a read data line on the ground potential side of the first and second read data lines becomes conductive, and the first or second bit line corresponding to the third or fourth transistor whichever has become conductive is driven to power supply potential.
Preferably, the write circuit drives one write data line of the first and second write data lines to power supply potential and the other write data line to ground potential, according to a logical level of a write data signal; and drives both of the first and second write data lines to power supply potential in write mask mode in which rewriting of data is inhibited. In this case, since no current flows out from a bit line pair and the read data line pair in write mask mode, a consumed current remains small in magnitude.